Folded DRAM CAM cell

ABSTRACT

A CAM device combines a folded bit line architecture with a standard six transistor DRAM based CAM cell and includes a sensing scheme where the active and reference bit lines being sensed are each from the same memory array of the CAM device. Noise present in one array therefore appears as common mode noise in both the active and reference bit lines, thereby permitting the sensing operation to be performed accurately even in the presence of increased noise.

FIELD OF INVENTION

The present invention relates generally to semiconductor memory devicesand, more particularly to sensing DRAM based content addressable memory(CAM).

BACKGROUND OF THE INVENTION

An essential semiconductor device is semiconductor memory, such as arandom access memory (RAM) device. A RAM allows a memory circuit toexecute both read and write operations on its memory cells. Typicalexamples of RAM devices include dynamic random access memory (DRAM) andstatic random access memory (SRAM).

Another form of memory is the content addressable memory (CAM) device. ACAM is a memory device that accelerates any application requiring fastsearches of a database, list, or pattern, such as in database machines,image or voice recognition, or computer and communication networks. CAMsprovide benefits over other memory search algorithms by simultaneouslycomparing the desired information (i.e., data in the comparand register)against the entire list of pre-stored entries. As a result of theirunique searching algorithm, CAM devices are frequently employed innetwork equipment, particularly routers and switches, computer systemsand other devices that require rapid content searching.

In order to perform a memory search in the above-identified manner, CAMsare organized differently than other memory devices (e.g., DRAM). Forexample, data is stored in a RAM in a particular location, called anaddress. During a memory access, the user supplies an address and writesinto or reads the data at the specified address.

In a CAM, however, data is stored in locations in a somewhat randomfashion. The locations can be selected by an address bus, or the datacan be written into the first empty memory location. Every memorylocation includes one or more status bits which maintain stateinformation regarding the memory location. For example, each memorylocation may include a valid bit whose state indicate whether the memorylocation stores valid information, or whether the memory location doesnot contain valid information (and is therefore available for writing).

Once information is stored in a memory location, it is found bycomparing every bit in memory with data in the comparand register. Whenthe content stored in the CAM memory location does not match the data inthe comparand register, the local match detection circuit returns a nomatch indication. When the content stored in the CAM memory locationmatches the data in the comparand register, the local match detectioncircuit returns a match indication. If one or more local match detectcircuits return a match indication, the CAM device returns a “match”indication. Otherwise, the CAM device returns a “no-match” indication.In addition, the CAM may return the identification of the addresslocation in which the desired data is stored or one of such addresses ifmore than one address contained matching data. Thus, with a CAM, theuser supplies the data and gets back the address if there is a matchfound in memory.

FIG. 1 is a circuit diagram showing a conventional DRAM-based CAM cell100, which includes two one-transistor (IT) DRAM cells 110 a and 110 b,and a four-transistor comparator circuit 120 made up of transistors Q2through Q6. DRAM cells 110 a and 110 b are used to store values.Generally, the content of cell 110 a is the logical NOT of the contentof cell 110 b. However, the cells 110 a, 10 b may also store the samevalues, i.e., “1”, “1”, or “0”, “0”, so that the CAM cell isrespectively set to “always match” or “always mismatch” states. DRAMcell 110 a includes transistor Q1 and a capacitor CA, which combine toform a storage node A that receives a data value from bit line BL1 atnode U during write operations, and applies the stored data value to thegate terminal of transistor Q2 of comparator circuit 120. Transistor Q2is connected in series with transistor Q3, which is controlled by a datasignal transmitted on data line D1, between a match line M and adischarge line D. The second DRAM cell 110 b includes transistor Q3 anda capacitor CB, which combine to form a storage node B that receives adata value from bit line BL2 at node V, and applies the stored datavalue to the gate terminal of transistor Q4 of comparator circuit 120.Transistor Q4 is connected in series with transistor Q5, which iscontrolled by a data signal transmitted on inverted data line D1#,between the match line and the discharge line.

FIG. 2 is a block diagram of a portion of a CAM device 200 whichincludes a plurality of CAM cells, such as the CAM cell 100 of FIG. 1.For purposes of simplicity, only a portion of the CAM device 200 isillustrated. In particular, some well known components, such as thepreviously discussed comparand register, control logic, and I/O logicare not illustrated. The device 200 includes two arrays 210 a, 210 b ofCAM cells 100. Each array 210 a, 210 b includes its own bit lines (e.g.,BL11-BL16 for array 210 a, BL21-BL26 for array 210 b) and word lines(e.g., WL11-WL13 for array 210 a). Each word line WL11-WL13, WL21-WL23is coupled a respective word line driver 220 a, 220 b. Similarly, eachbit line is also coupled to respective bit line drivers (notillustrated) The CAM device 200 also includes a plurality of senseamplifiers 230. Each sense amplifier 230 is coupled to the CAM cells 100of two separate bit lines (e.g., bit lines BL11, BL21) from twodifferent arrays. This type of architecture, where a sense amplifier iscoupled to bit lines from different arrays, is known as an open bit linearchitecture.

Now referring back to FIG. 1, in order perform a write operation upon aCAM cell, the data values (which are complements) to be stored arcrespectively written to dynamic storage nodes A and B by applyingappropriate voltage signals (e.g., Vcc for logical ‘1’ or ground forlogical ‘0’) on bit lines BL11 and BL21, and then applying a highvoltage signal on word lines WL1 and WL2. The high voltage on word linesWL1 and WL2 turn on transistor Q1 and Q2, thereby passing the voltagesignals to dynamic storage nodes A and B. Refresh circuitry (notillustrated), periodically refreshes the charges stored in capacitors CAand CB, so the data does not decay over time.

In order to perform a match operation, the data stored at nodes A and Bare respectively applied to the gate terminals of transistors Q2 and Q5of comparator circuit 120. Comparator circuit 120 is utilized to performmatch (comparison) operations by, for example, precharging the matchline M, grounding the discharge line D, and transmitting an applied datavalue and its complement respectively on data lines D1 and D1# to thegate terminals of transistor Q3 and Q6, respectively. A no-matchcondition is detected when match line M is discharged to ground throughthe signal path formed by transistors Q2 and Q3 and the discharge lineD, or through the signal path formed by transistors Q5 and Q6 and thedischarge line D. For example, when the stored data value at node A andthe applied data value transmitted on data line D1# are both logic “1”,then both transistors Q2 and Q3 are turned on to discharge match line Mto the discharge line (e.g., ground). When a match condition occurs,match line M remains in its pre-charged state (i.e., no signal path isformed by transistors Q2 and Q3, or transistors Q5 and Q6).

In order to perform a read operation, data stored as a charge level inthe capacitors CA, CB of one of the dynamic storage nodes A, B of theCAM cell 100 is sensed using an associated sense amplifier 230 (FIG. 2)which compares the voltage level of a bit line coupled to one of thedynamic storage nodes (known as the active bit fine) with the voltagelevel of a bit line not coupled to any dynamic storage nodes (known asthe reference bit line). For example, node A of the CAM cell 100 whichappears as the top left CAM cell illustrated in FIG. 2 can be sensed byfirst precharging two bit lines. The two bit lines to be prechargedwould include the bit line BL11 which will couple the CAM cell 100 tothe sense amplifier 230 (i.e., the active bit line), as well as theother bit line BL21 coupled to the same sense amplifier 230 (i.e., thereference bit line). As illustrated in FIG. 2, each sense amplifier hasone input coupled to a bit line of array 210 a and another input coupledto a corresponding bit line of array 210 b. The word line WL13associated with the CAM cell 100 would then be charged, causing thetransistor Q1 in the CAM cell 100 to conduct and thereby share thecharge of capacitor CA with bit line BL1. The charge sharing alters thevoltage level of bit line BL11. The sense amplifier 230 is then used todetect the change in potential between BL11 and BL21. The senseamplifier outputs an indication of the state stored at storage node A asa signal indicating the relative potential difference between bit linesBL11 and BL21 on line 235.

The performance of the above described read operation suffers from manynoise issues since the sensing mechanism relies on the reference andactive bit lines to be from two separate arrays of the device during asensing operation. As CAM devices increase in density and thereforepower consumption, the level of noise within a CAM cell is likely toincrease. There is therefore a need for a CAM device architecture whichhas better noise immunity.

SUMMARY OF THE INVENTION

The present invention is directed to a CAM device which combines afolded bit line architecture with a standard six transistor DRAM basedCAM cell. The CAM device of the present invention has a sensing schemewhere the active and reference bit lines being sensed arc each from thesame memory array of the CAM device. Noise present in one arraytherefore appears as common mode noise in both the active and referencebit lines, thereby permitting the sensing operation to be performedaccurately even in the presence of increased noise.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other advantages and features of the invention willbecome more apparent from the detailed description of exemplaryembodiments of the invention given below with reference to theaccompanying drawings, in which:

FIG. 1 is a circuit diagram of a conventional six transistor DRAM basedCAM cell;

FIG. 2 is a block diagram illustrating a conventional CAM device usingan open bit line scheme;

FIG. 3A is a block diagram illustrating a CAM device in accordance witha first embodiment of the present invention;

FIG. 3B is a block diagram illustrating a CAM device in accordance witha second embodiment of the present invention;

FIG. 4 is a circuit diagram of modified sense amplifier circuit usedwith the CAM device of FIG. 3; and

FIG. 5 is a block diagram of a processor based system utilizing the CAMdevice of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Now referring to the drawings, where like reference numerals designatelike elements, there is shown in FIG. 3A a block diagram illustratingone embodiment of a CAM device 300 in accordance with the principles ofthe present invention.

The device 300 is illustrated as having two arrays 210 a, 210 b of CAMcells 100. For purposes of simplicity, only a portion of the CAM device300 is illustrated. In particular, some well known components, such asthe comparand register, control logic, and I/O logic are notillustrated. It should be noted that the invention may be practiced evenif the number of arrays is varied. Each array 210 a, 210 b is comprisedof a plurality of CAM cells 100, which preferably are of the sixtransistor DRAM based embodiment previously discussed in connection withFIG. 1. Each CAM cell 100 is located at an intersection of a word line(e.g., WL11) and a bit line (e.g., BL11). Each word line is also coupledto a word line driver 220 a, 220 b. Each bit line is also coupled to abit line driver (not illustrated) and a sense amplifier circuit 231.

Now referring also to FIG. 4, it can be seen that the sense amplifiercircuit 231 is coupled to four inputs BLA, BLB, BLC, and BLD. The senseamplifier 231 includes a front-end circuit 233 comprising multiplexers232 a, 232 b, and select signal input sel. (The sel signal can becontrolled by the control circuit, which as noted above, is notillustrated in the drawings.) The two multiplexers 232 a, 232 b arecontrolled based on the state of the sel signal so that either signalsBLA/BLC or signals BLB/BLD are selected for sensing by the senseamplifier 230. The result of the sensing is output on line 235.

FIG. 3B is an illustration of the CAM device 300 built in accordancewith a second embodiment of the present invention. The CAM device 300 ofFIG. 3B differs from that illustrated in FIG. 3A by using pairs of senseamplifiers 230 instead of the single sense amplifier circuit 231. Theembodiment illustrated in FIG. 3B therefore does not require the use ofa sel control line for controlling the multiplexers 232 a, 232 b (FIG.4) corresponding to the sense amplifier circuit 231 of FIG. 3A. However,the embodiment shown in FIG. 3B requires using twice as many senseamplifiers 230.

Thus, one significant difference between device 300 and prior artdevices (e.g., device 200) is that each sensing operation is performedusing an active and a reference bit line from the same array (e.g., 210a). By always sensing two lines from the same array, any noise whichappears only in one array is less likely to disrupt the sensingoperation because the noise will appears as common mode noise acrossboth the active and reference bit lines, thereby identically affectingthe potential of the active and reference bit lines, and having noeffect on the potential difference at any point in time between theactive and reference bit lines. This property permits the use ofordinary sense amplifiers, even in higher level noise environments. Bycontrast, if an open bit line architecture were used, noise present inone array may result in an incorrect sensing operation.

FIG. 5 is an illustration of a processor based system 500 including achip 300 in accordance with the present invention. The system 500includes a central processing unit (CPU) 510, a main memory 502, atleast one mass storage device 503, at least peripheral devices 504-505(e.g., keyboard and display), and a CAM subsystem 506. The CAM subsystem506 includes a plurality of CAM devices 300 of the present invention.

An example of a processor based system 500 may be a network router, inwhich case peripheral devices 504-505 may be network cards attached todifferent computer networks. The main memory 502 may include a randomaccess memory for storing data, and a read only memory for storing aboot loader, and the mass storage device 503 may store an operatingsystem and application software for the router. The CAM subsystem 506may be used to store network routing table.

While the invention has been described in detail in connection with theexemplary embodiment, it should be understood that the invention is notlimited to the above disclosed embodiment. Rather, the invention can bemodified to incorporate any number of variations, alternations,substitutions, or equivalent arrangements not heretofore described, butwhich are commensurate with the spirit and scope of the invention.Accordingly, the invention is not limited by the foregoing descriptionor drawings, but is only limited by the scope of the appended claims.

1. A content addressable memory comprising: a plurality of memoryarrays, each comprising a plurality of bit lines; a plurality of wordlines, intersecting the plurality of bit lines; a plurality of CAMcells, each disposed at an intersection of a bit line and a word line;and a plurality of sense amplifiers, wherein each of said plurality ofsense amplifiers is operated to sense a potential difference between twobit lines from a same one of said plurality of memory arrays; and aswitching circuit to selectively couple each one of the plurality ofsense amplifiers to two bits lines from a first one of said plurality ofmemory arrays or two bit lines from a second one of said plurality ofmemory arrays.
 2. The content addressable memory of claim 1, whereinsaid switching circuit comprises a pair of multiplexers.
 3. The contentaddressable memory of claim 1, wherein each sense amplifier is disposedbetween said first and second ones of said plurality of memory arrays.4. A content addressable memory comprising: a plurality of memoryarrays, each comprising a plurality of bit lines; a plurality of wordlines, intersecting the plurality of bit lines; a plurality of CAMcells, each disposed at an intersection of a bit line and a word line;and a plurality of sense amplifiers, each of said plurality of senseamplifiers being disposed between two of said plurality of memoryarrays; wherein each of said plurality of sense amplifiers is operatedto sense a potential difference between two bit lines from a same one ofsaid plurality of memory arrays.
 5. A processor based system,comprising: a bus; a processor, coupled to said bus; a main memory,coupled to said bus; a content addressable memory, coupled to said bus,said content addressable memory comprising: a plurality of memoryarrays, each comprising a plurality of bit lines; a plurality of wordlines, intersecting the plurality of bit lines; a plurality of CAMcells, each disposed at an intersection of a bit line and a word line;and a plurality of sense amplifiers, wherein each of said plurality ofsense amplifiers is operated to sense a potential difference between twobit lines from a same one of said plurality of memory arrays; and aswitching circuit to selectively couple each one of the plurality ofsense amplifiers to two bits lines from a first one of said plurality ofmemory arrays or two bit lines from a second one of said plurality ofmemory arrays.
 6. The system of claim 5, wherein said switching circuitcomprises a pair of multiplexers.
 7. The system of claim 5, wherein eachsense amplifier is disposed between said first and second ones of saidplurality of memory arrays.
 8. A processor based system, comprising: abus; a processor, coupled to said bus; a main memory coupled to saidbus; a content addressable memory, coupled to said bus, said contentaddressable memory comprising: a plurality of memory arrays, eachcomprising a plurality of bit lines; a plurality of word lines,intersecting the plurality of bit lines; a plurality of CAM cells, eachdisposed at an intersection of a bit line and a word line; and aplurality of sense amplifiers; wherein each of said plurality of senseamplifiers is operated to sense a potential difference between two bitlines from a same one of said plurality of memory arrays and whereineach of said plurality of sense amplifiers is disposed between two ofsaid plurality of memory arrays.
 9. A processor based system,comprising: a bus; a processor, coupled to said bus; a main memory,coupled to said bus; a content addressable memory, coupled to said bus,said content addressable memory comprising: a plurality of memoryarrays, each comprising a plurality of bit lines; a plurality of wordlines, intersecting the plurality of bit lines; a plurality of CAMcells, each disposed at an intersection of a bit line and a word line;and a plurality of sense amplifiers; wherein each of said plurality ofsense amplifiers is operated to sense a potential difference between twobit lines from a same one of said plurality of memory arrays; a firstnetwork interface, coupled to said bus and a first network; and a secondnetwork interface, coupled to said bus and a second network; whereinsaid system is operated to route network traffic between said first andsecond networks.
 10. The system of claim 9, wherein said contentaddressable memory stores routing information.
 11. A method foroperating a content addressable memory having a plurality of arrays ofCAM cells, comprising: precharging a reference bit line; precharging anactive bit line; coupling a storage capacitor of a CAM cell to saidactive bit line; and sensing a potential difference between saidreference bit line and said active bit line; wherein said reference bitline and said active bit line are from a same array of said contentaddressable memory.
 12. The method of claim 11, wherein said step ofsensing comprises: coupling said reference bit line and said active bitline to a sense amplifier; and operating said sense amplifier to sensethe potential difference between said active bit line and reference bitline.
 13. The method of claim 11, wherein said step of sensingcomprises: coupling one pair of bit lines from a plurality of pairs bitlines as the reference bit line and active bit line to a senseamplifier; and operating said sense amplifier to sense the potentialdifference between said active bit line and reference bit line.
 14. Themethod of claim 13, wherein said coupling one pair of bit linescomprises: controlling a first multiplexer coupled to a first bit linefrom a first array and a first bit line from a second array; andcontrolling a second multiplexer coupled a second bit line from thefirst array and a second bit line from the second array; wherein saidfirst and second multiplexers are controlled to select a pair of bitlines from a same one of said first and second arrays.